The present inventive embodiments relate to semiconductor circuits, and more particularly, to a dynamic flip flop having a data independent P-stack feedback mechanism, which may integrate a single stage combinational circuit.
A conventional flip flop is a common component used in many integrated circuits. In the ever-growing complex architectures, scenarios of multiple signals converging onto a single flip flop are increasing at an exponential rate. With higher frequency targets, negative setup slack (i.e., data arriving later than the clock arrival) of a path is becoming a bottleneck in many designs. To deal with these and other growing problems, flip flops must be fast and have setup benefit.
For example, when an output of an N:1 multiplexor (MUX) is stitched to a data input pin of a flip flop, an evaluation of the N:1 MUX is the main contributor to a setup requirement of the circuit. In one approach to ameliorating the setup requirement, the N:1 MUX may be integrated into the flip flop. However, with a larger number of inputs N to the MUX, a larger number of signals may converge into the flip flop, and a P-stack in a feedback circuit will become N+2 high. In other words, the P-stack is taller and the N-stack is wider. This increases the total capacitance on internal nodes within the circuit.
What is needed is an improved dynamic flip flop having a data independent P-stack feedback mechanism.